Semiconductor device with built-in scan test circuit

ABSTRACT

The clock cycle during the shift operation is set shorter than the clock cycle during the capture operation in the scan test circuit. For example, the clock cycle during the shift operation is set to 20 nano second, while the clock cycle during the capture operation is set to 100 nano second. The clock is fed from a LSI tester outside of the LSI through the clock terminal CLK. The cycle of the clock can be switched to synchronize with the change of the scan enable signal SCANEN by the LSI tester. The time for shift operation can be shortened in this invention, leading to the shorter scan test time.

CROSS-REFERENCE OF THE INVENTION

This invention is based on Japanese Patent Application No. 2004-333913,the content of which is incorporated herein by reference in itsentirety.

BACKGROUND OF THE INVENTION

1. Field of Invention

This invention relates to a scan test circuit for simplifying the testof a large scale integrated circuit.

2. Description of Related Art

Testing by a LSI tester is usually performed when a large scaleintegrated circuit (referred to as LSI hereinafter) is shipped to themarket. The objective of the test pattern for this testing is to finddefects in a plurality of the logic circuits that configures a LSI asmuch as possible.

However, as the scale of LSI gets larger, the larger test vector andlonger testing time are required to perform the test on the entire logiccircuits. The circuit design for testability has been sought for solvingthis problem.

The design for testability is the designing method where the teststrategy is determined while a LSI is designed, and where the testcircuit has been built-in in the LSI. The basic criteria for easytesting include the observability and controllability. When a circuithas a good observability, it is easy to observe the logical value of anode in the circuit. And, it is easy to determine a logical value of anode in the circuit through the data inputted from outside when acircuit has a good controllability. The better observability andcontrollability of a circuit leads to the more efficient test pattern,and as a result, leads to the improved defect detection of the logiccircuits. One of the test circuits with the improved observability andcontrollability is a scan test circuit.

A scan test circuit is the circuit which has a flip flop circuitcorresponding to each of the logic circuits in a LSI. A plurality offlip flop circuits are connected in a chain form, configuring a shiftresistor that performs shift operation for consecutively shifting thedata coming into the flip flop circuit and capture operation forcapturing the output of each of the logic circuits into each of the flipflop circuits.

That is, the data of each of the flip flop circuits is sent as a testsignal to each of the logic circuit through the first shift operation,and the output data of each of the logic circuits is captured by each ofthe flip flop circuits through the next capture operation. Then, theoutput data from each of the logic circuits captured by each of the flipflop circuits is chronologically acquired from the last row of the flipflop circuit through the next shift operation. The testing is performedby comparing the output data of each of the logic circuits acquired inthe manner described above with the expected values. Japanese PatentApplication No. 2001-59856 is the technical document that relates tothis invention.

However, the scan test circuit that repeats the shift operation and thecapture operation takes longer testing time and requires higher testingcost. Especially, the shift operation should be repeated as many timesas the number of the flip flops that configures the shift resistor,taking most of the test time.

SUMMARY OF THE INVENTION

The invention provides a semiconductor device with a built-in scan testcircuit having a plurality of logic circuits and a scan flip flopcircuit provided for each of the logic circuits and receiving a scansignal. The scan flip flop circuit includes a shift resistor thatperforms a shift operation according to a first clock when the scanenable signal is at a first level and performs a capture operation tocapture an output data of a corresponding logic circuit according to asecond clock when the scan enable signal is at a second level, and thefirst clock is shorter than the second clock.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an embodiment of the scan testcircuit of this invention.

FIG. 2 is the diagram showing the operation mode of an embodiment of thescan test circuit of this invention.

FIG. 3 is a clock waveform diagram of the scan test circuit of priorarts.

FIG. 4 is a clock waveform diagram of an embodiment of the scan testcircuit of this invention.

DETAILED DESCRIPTION OF THE INVENTION

The scan test circuit of this invention will be explained by referringto the drawings.

FIG. 1 is a circuit diagram showing the scan test circuit of anembodiment of this invention. First, second and third scan flip flopcircuits, SFF1, SFF2, and SFF3 are disposed between first, second,third, and fourth logic circuits, LG1, LG2, LG3, LG4 respectively. Thefirst, second third and fourth logic circuits LG1, LG2, LG3, LG4 arebased on a combination of logic circuits including AND circuit and NANDcircuit.

The first scan flip flop circuit SFF1 has a first multiplexer MPX1 and aD type flip flop circuit FF1 (delayed flip flop circuit). The firstmultiplexer MPX1 selects a scan test signal from a data input terminalDIN or an output of the first logic circuit LG1 corresponding to thescan test signal according to a scan enable signal SCANEN, and thenoutputs the selected signal to the input terminal D of the first D typeflip flop circuit FF1.

The second scan flip flop circuit SFF2 has a second multiplexer MPX2 anda second D type flip flop circuit FF2. The second multiplexer MPX2selects the scan test signal from the first scan flip flop circuit SFF1at the previous row or an output of the second logic circuit LG2corresponding to the scan test signal according to the scan enablesignal SCANEN, and then outputs the selected signal to the inputterminal D of the second D type flip flop circuit FF2.

The third scan flip flop circuit SFF3 has a third multiplexer MPX3 and athird D type flip flop circuit FF3. The third multiplexer MPX3 selectsthe scan test signal from the second scan flip flop circuit SFF2 at theprevious row or an output of the third logic circuit LG3 correspondingto the scan test signal according to the scan enable signal SCANEN, andthen outputs the selected signal to the input terminal D of the third Dtype flip flop circuit FF3.

Clock input terminals C of the first, second and third D type flip flopcircuits FF1, FF2, FF3 receive the common clock signal from a clockterminal CLK. Although only three logic circuits and three scan flipflop circuits are shown in the FIG. 1, the number of the logic circuitsand its corresponding scan flip flop circuits ranges from severalthousands to several ten thousands in an actual LSI.

A selector SEL1 selects the scan test signal from the third scan flipflop circuit SFF3 at the previous row or an output of the third logiccircuit LG3 corresponding to the scan test signal according to a scanenable signal SCANEN, and then outputs the selected signal to a dataoutput terminal Dout.

Next, operation of the scan test circuit described above will beexplained by referring to FIG. 2. The scan test circuit is set as ashift mode when the scan enable signal SCANEN is at high level. That is,the first multiplexer MPX1 selects the scan test signal from the inputterminal DIN1, the second multiplexer MPX2 selects the scan test signalfrom the first scan flip flop circuit SFF1, the third multiplexer 3 MPX3selects the scan test signal from the second scan flip flop circuitSFF2, and the selector SEL1 selects the scan test signal from the thirdscan flip flop circuit SFF3.

The first, second, and third D type flip flop circuits FF1, FF2, FF3 areconnected in a chain form, configuring a shift resistor. Therefore, thescan test signal from the data input terminal DIN1 is consecutively fedfrom the output terminal Q of the D type flip flop circuit to the inputterminal of the next D type flip flop circuit at each clock inputtedfrom the clock input terminal. That is, a shift operation is performedfor the time corresponding to the three-clock time.

Next, the scan test circuit is set as a capture mode when the scanenable signal SCANEN changes to low level. That is, the firstmultiplexer MPX1 selects the output data from the first logic circuitLG1, the second multiplexer MPX2 selects the output data from the secondlogic circuit LG2, the third multiplexer MPX3 selects the output datafrom the third logic circuit LG3, and the selector SEL1 selects theoutput data from the fourth logic circuit LG4.

The output data from the first, second and third logic circuits LG1,LG2, LG3 are captured by and kept at the first, second and third D typeflip flop circuit FF1, FF2, and FF3 respectively. The first, second andthird D type flip flop circuits FF1, FF2, FF3 receive each of the outputdata simultaneously. Therefore, all the operation for keeping the entiredata is done for the time equivalent to one-clock time.

Then, the scan test circuit is set back as shift mode when the scanenable signal SCANEN changes to high level. The first, second, and thirdD type flip flop circuits FF1, FF2, FF3 are connected in a chain form,configuring a shift resistor again. Therefore, the output data from thefirst, second and third logic circuits LG1, LG2, LG3 that are kept atthe first, second and third D type flip flop circuits FF1, FF2, and FF3are shifted for each clock inputted from the clock input terminal CLKand each output data can be observed chronologically at the data outputterminal Dout. Then, the testing is performed by comparing the outputdata of each of the logic circuits acquired in the manner describedabove to the expected value.

In this embodiment, the clock cycle is shortened during the shiftoperation compared to the clock cycle during the capture operation. Incomparison, the clock cycle during the shift operation is the same asthat during the capture operation in the conventional scan testcircuits, as shown in FIG. 3. The clock cycle is determined to assurethe time enough for the capture operation, for example, 100 nano second.

However, the cycle of the clock during the shift operation is shorterthan the cycle of the clock during the capture operation in thisembodiment, in recognition that it is possible to operate the shiftresistor faster during the shift operation than during the captureoperation, as shown in FIG. 4. For example, the cycle of the clock isset to 20 nano second for the shift operation, while the cycle of theclock is set to 100 nano second for the capture operation.

The clock is fed from a LSI tester outside of the LSI through the clockterminal CLK. The cycle of the clock can be switched to synchronize withthe change of the scan enable signal SCANEN by the LSI tester. The timefor shift operation can be shortened in this manner in this invention,leading to the shorter scan test time.

1. A semiconductor device with a built-in scan test circuit, comprising:a plurality of logic circuits; and a scan flip flop circuit provided foreach of the logic circuits and receiving a scan signal; wherein the scanflip flop circuit comprises a shift resistor that performs a shiftoperation according to a first clock when the scan enable signal is at afirst level and performs a capture operation to capture an output dataof a corresponding logic circuit according to a second clock when thescan enable signal is at a second level, and the first clock is shorterthan the second clock.
 2. The semiconductor device of claim 1, whereinthe capture operation is performed for a period of one clock.
 3. Thesemiconductor device of claim 1, wherein the scan flip flop circuitfurther comprises a multiplexer selecting the output of thecorresponding logic circuit when the scan enable signal is at the secondlevel and selecting the output of a scan flip flop circuit positionedprior to the scan flip flop circuit in a shift operation sequence whenthe scan enable signal is at the first level.